1. Technical Field
The present invention relates generally to electronic circuit design, and more particularly to a system, method, program product and database for electronic circuit design.
2. Related Art
Electronic circuits are often designed using automated design systems to increase the speed of the design process, and to allow evaluation of a design prior to actual production. In a conventional setting, a designer uses the automated design system to generate a circuit by inputting data at a computer workstation. A designer will typically design a circuit in terms of functional aspects and then deconstruct each aspect into ever-smaller features. For example, a designer may establish a functional aspect and then draw several simple features in laying out components for the functional aspect, and may free-hand a number of larger more unique features to handle special circumstances. Layout of features providing the functional aspects of the circuit may be spread out over numerous layers. A design ultimately results in a design file that includes instructions on how the circuit features are laid out over a design grid(s) that maps features' relative positions.
Although automated design systems provide substantial support to designers, the ever-increasing complexity of circuits has resulted in design instruction files of extremely large proportions. The large design instruction files strain resources in a number of ways. First, automated design system performance resources must be continuously increased to sustain preferred speed. Second, storage requirements of the myriad of design feature instructions and the design instruction files must continuously be increased. As a result, the expense of design workstations and related storage facilities has become an increasing problem.
One reason for such large design instruction files is that the data for design implementation is presented in the form of an extremely long instruction list that an automated design system can use to generate the design. Unfortunately, each time a feature is required in a design, its respective instruction portion is repeated in the instruction list. That is, each feature has all instructions (data) required for its implementation present in the instruction list every time the feature is required. Each feature's instruction portion may include, for example: its shape, which net it's on, which layer it's on, etc. This redundant usage of instruction portions occurs despite the fact that most designers create designs that have a fairly low number of unique features. For example, even for complex designs such as a multiple level ceramic design having, for example, 12,123,402 total features, the number of uniquely shaped features may be relatively small, e.g., 5147.
One approach used to limit the size of design data is to have placement instructions for each feature based on a previous structure's location. Accordingly, each instruction list must be maintained as an integrated unit such that each feature's position relative to a prior feature can be determined. This situation presents a number of drawbacks. First, compartmentalizing the instruction list and removing data from the list are slow. Second, evaluating a single feature, e.g., for capacitance, that is within the instruction list, e.g., feature 10 million, requires computation beginning at the first feature.
Another problem with the conventional design instruction file is created by the fact that each feature may have its own peculiarities requiring less or more data. For example, a simple structure may require 4 bytes, while a complex structure may require 15 bytes. The instruction list thus includes a variety of data width formats. This causes, a standard processor that is based on 4 byte or 8 byte multiples, e.g., a 32 bit or a 64 bit processor, to process data inefficiently.
One approach to address the above issues is referred to as the “Gerber format,” the most recent version of which is referred to as the RS274X format, which was developed by Gerber Systems, now part of Mania Barco. The Gerber format provides a means of transferring printed circuit board information devices that convert the electronic printed circuit board (PCB) data to artwork produced by a photo-plotter. As part of this format, an aperture list is implemented for recalling particular apertures to generate features, copies of which are used in the design. Unfortunately, this format suffers from a number of drawbacks in use as a design system. First, it is ASCII based, which greatly increases data instruction file size. Second, instruction lists are limited to shape characteristics only. Accordingly, data regarding net, layer characteristics, materials, specific capacitance, etc., are not expressible, and are not included. As a result, the Gerber format is not appropriate for design database use.
Another approach to the above issues is used in the IBM Graphics Language 1 (GL1). The GL1 language specifies a given feature by one of two methods. First, the location and geometric parameters for a given unique feature shape must be placed in memory at least once. The amount of memory required for a given feature shape is a function of it's complexity, for instance, a square requires only 4 numbers (X, Y, width, height) whereas a 60 sided polygon requires 120 numbers (X and Y for each of the 60 corners). The GL1 language allows further copies of the shape to be used by nesting the original copy. The nested copies are each stored as a variable width name data object. The second way another copy of a shape can be recorded is to create a new feature, with the attendant memory requirement. For example, a semiconductor design of a 60-sided polygon may require a feature to be created, for example, 1531 separate times. The GL1 language has all of the features stored as variable width data objects, which is inefficient because either a look up table of memory locations for features must be created and maintained, or serial reading of the entire feature list need be undertaken to access a given feature.
In view of the foregoing, there is a need in the art for an improved electronic circuit design methodology, system and product that does not suffer from the problems of the related art.